This invention relates to a semiconductor device, and in particular, to a semiconductor device for producing a high output such as a power MOS transistor and an insulating gate bipolar transistor.
In a semiconductor device having a high output of the type as mentioned above, a plurality of unit devices, which are called cells and each of which has the same structure, are formed on a surface of a substrate in a matrix form. Further, an electrode common to all cells is formed thereon.
In a conventional method of taking out an electrode, the electrode on the cell is taken out and placed onto a bonding pad, on which the cell is not being formed, to connect the bonding pad with a bonding wire for connecting an external portion.
However, in the recent cases, the bonding pad is directly placed on a cell region so that the on-resistance as well as the size of a chip is much more reduced.
Referring to FIG. 1, description will be made about a power MOS transistor according to a first related art.
As illustrated in FIG. 1, a nxe2x88x92 type epitaxial layer 2 is formed on a n+ type silicon substrate 1, and a p-type base layer 6 doped with p-type impurity is formed on a surface of the nxe2x88x92 type epitaxial layer 2.
Further, a trench 3 is opened so as to reach the nxe2x88x92 type epitaxial layer 2 from the substrate surface. After a gate oxide film 4 due to a thermal oxidation process is formed for an internal surface of the trench 3, a gate electrode 5 formed by polysilicon is buried in the trench 3.
Further, a n+ source region 7 is formed around the gate electrode 5. An interlayer film 8 is formed on the gate electrode 5 to insulate and separate the gate electrode 5.
Moreover, an Al electrode layer 13 serving as a source bonding pad is formed on the substrate such that the source region 7 is short-circuited by the base layer 6.
In the meantime, a drain electrode 11 is formed at a back surface of the substrate.
In such a MOS transistor, the drain electrode 11 is bonded on a die pad (not shown), and the Al electrode layer 13 is coupled to a source lead (not shown) by the use of an Au bonding wire 12. Alternatively, an Al bonding wire may be used in lieu of the Au bonding wire.
The semiconductor device having such an Al electrode layer (namely, a bonding pad) is, for example, disclosed in Japanese Unexamined Patent Publication No. Hei. 2-308539 (which is, Japanese Patent No. 2756826), Japanese Unexamined Patent Publication No. Hei. 5-175273, and Japanese Unexamined Patent Publication No. Hei. 10-12571.
Herein, a side which is brought into contact with a semiconductor substrate is made of Al including Si, while a wire-bonded side is made of Al as described in the above-mentioned Japanese Unexamined Patent Publication No. Hei. 2-308539.
Further, an Al underlayer is formed between gate electrodes so that a surface of an Al electrode layer is lowered on the gate electrode in the above Japanese Unexamined Patent Publication No. Hei. 5-175273.
In addition, an Al electrode having a silicon content of 0.1% or less is provided on a silicide layer as described in the above-mentioned Japanese Unexamined Patent Publication No. Hei. 10-12571.
However, in the electrode structure of this type, the Au Al alloy formed under the Au disadvantageously leads to the breakage of the transistor cell of the underlayer when the Au wire is bonded on the electrode layer. Consequently, this brings about the problem such as a leak, a short, or the like.
As illustrated in FIG. 2, the bonding process is carried out by applying pressure to the wire by a capillary under a heating process (this method is referred as to a thermo-compression bonding method).
Alternatively, the bonding process is performed by applying a supersonic vibration for the wire (this method is referred to as a supersonic thermo-compression bonding method).
When the bonding process is carried out, an Au4Al layer 14 is first formed at a contact surface between the wire and the Al electrode. Further, Au is further diffused from the Au4 Al layer 14 into an internal portion. Thereby, an Au5 Al2 layer 15 is formed in an internal portion of the Al electrode.
As an alloy process proceeds, the interlayer film 8 is subjected to stress, and thereby, a crack 16 often occurs. In consequence, a breakdown voltage between the gate electrode 5 and the Al electrode layer 13 is degraded, and further, a short takes place.
Moreover, the surface of the silicon substrate is subjected to the stress by the alloy process during the bonding process, and thereby, a leak current is increased.
In addition, an alloy spike 17 is often generated by a reaction between the Al electrode layer 13 and the underlayer silicon directly under the bonding wire when the conventional semiconductor is kept at a high temperature between 150xc2x0 C. and 175xc2x0 C.
Under this circumstance, the alloy spike 17 often reaches the nxe2x88x92 type epitaxial layer 2 through the p-type base layer 6. Consequently, the short-circuit accidentally occurs.
It is therefore an object of this invention to provide a semiconductor device which is capable of preventing an Al electrode layer being alloyed when an Au wire is bonded for an Al electrode layer on a cell in a semiconductor device having a high output, for example, a power MOS transistor.
It is another object of this invention to provide a semiconductor device which is capable of preventing growth of an alloy spike from an Al electrode under high temperature atmosphere.
According to this invention, a semiconductor device has a semiconductor substrate. An active region is formed on the semiconductor substrate. An electrode layer is directly formed on the active region and serves as a bonding pad.
With such a structure, the electrode layer is mainly formed by an Al alloy layer containing Cu.
In this event, the Al alloy layer is formed by an AlCu alloy or an AlSiCu alloy. The Al alloy layer preferably has a film thickness which is 2.5 xcexcm or more.
Further, the Al alloy layer preferably has a Cu content which falls within the range between 0.1 and 5 weight %.
The electrode layer is formed by a laminate layer consisting of the Al alloy layer and a barrier layer. In this condition, the barrier layer is placed under the Al alloy layer.
In this case, the barrier layer is formed by a TiN/Ti layer or a TiN layer.
Alternatively, the barrier layer may be formed by a silicide layer having a high melting point.
The semiconductor device preferably produces a high output.
Such a semiconductor device includes a power MOS transistor or an insulating gate bipolar transistor.
More specifically, the bonding pad is formed on the cell transistor by the use of the Al alloy containing Cu. Consequently, the Al electrode can be effectively suppressed being alloyed into the Auxe2x80x94Al when the Au wire is bonded.
Thereby, the stress applied to the interlayer film during the wire bonding process can be suppressed. Further, the leak and short-circuit can be prevented. It is to be noted here that the leak and short-circuit are generated when the interlayer film is subjected to the damage.
Moreover, the barrier layer consisting of the TiN/Ti layer is formed under the Al electrode layer containing Cu. In consequence, the growth of the alloy spike can be suppressed even when the substrate is kept under the high temperature. As a result, the reliability can be enhanced for a long time.